= MOSIS and CMP multiproject chip tests =
=== MOSIS ===
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Chips for [[HitchhikerTest| Hitchhiker test]].  Presume 10 chips driving 16 slots each per thinsat, 80 thinsats, 1000 chips before test, defective chips simulate radiation damage and will be used for radiation and life test.  24 GHz switched slot instead of 70 GHz.

Although the chips will have lots of small column grid pads, we can test them with 12 very large center-of-chip probe pads connected to power/ground and an IEEE 1149.4 mixed signal scan bus, and two differential RF ports.

At 100 micrometer pad pitch, that is 140 pins per die.  Many pins will be available for redundant interconnect, and perhaps 40 for pin drivers for third party test chips, crossbarred to voltage and current sources for crude analog tests.

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== MOSIS ==
http://www.mosis.com/products/fab-processes

=== MOSIS TSMC ===
 * https://www.mosis.com/db/pubf/fsched?ORG=TSMC
 * 28nm / 40nm / 45nm / 65nm
 * Minimum chip is 12 mm^2^, assume 5 mm x 2.4 mm padzilla
||<-8> MOSIS automated quotes                                                                            ||
|| Quote    || Process    || X size || Y size || quantity || first hundred || next hundred || total cost ||
|| 176708-A || 65nm LP    || 5000   || 2400   || 500      ||  83,000       || 11,000       || 127,000    ||
|| 176707-A || 65nm LP    || 4000   || 3000   || 500      ||  83,000       || 11,000       || 127,000    ||
|| 176706-A || 65nm LP    || 5000   || 5000   || 500      || 172,917       || 11,000       || 216,917    ||
|| 176705-A || 65nm LP RF || 2000   || 2000   || 500      ||  83,000       || 12,000       || 131,000    ||
|| WAG      || 65nm LP    || 5000   || 2400   || 1000     ||  83,000       || 11,000       || 182,000    ||
 

=== MOSIS IBM ===
https://www.mosis.com/vendors/view/ibm


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== CMP France ==