Integrated Circuit Mass

How Much does a Chip Weigh?

CMOS (Complimentary Metal Oxide Semiconductor) integrated circuit chips are made N type and P type MOS field effect transistors, wiring, insulators, on top of a silicon substrate. The zoo of devices on all varieties of integrated circuits includes bipolar transistors, diodes, capacitors, loop inductors, diffused and thin-film resistors, sometimes even special sensors like avalanche photodiodes. However, almost everything we do with server sky will involve advanced-process CMOS, with some DRAM ( Dynamic Random Access Memory ) using stack capacitors and some flash (block rewritable) EEPROM ( Electrically Eraseable Programmable Read Only Memory, which writes information by trapping charges in the insulators of MOS gates. IBM 3.jpg

These are all planar processes produced by photolithography. All structures are made by deposition and etching of materials, and are typically very thin, a few micrometers. High power integrated circuits, such as 150 watt microprocessors and GPUs, are somewhat thicker, because the uppermost layers of interconnect metal are thick and low resistance to handle up to 100 amps of power. The lower signal handling metal layers are thin and optimized for low capacitance wires, perhaps half as thick as they are wide (a fraction of a micrometer).

This very complex stack shows 5 bottom layers of very thin, narrow metal for local interconnect, 4 middle layers of "long distance" signal wiring, two layers of thick wires for power and clock, and one very fat layer for power.

The scanning electron micrograph shown here has all the bells and whistles, including "trench capacitors" to reduce power line noise and "through silicon vias" to connect to wiring underneath. All these "process adders" cost money, fabrication time, and yield, and are available if really necessary but we will try to avoid them.

Server sky chips will use low power varieties of these advanced processes, with fewer metal layers and no fat upper layers because each chip will be small and use milliamps rather than amps. We can expect the thickness of the active layers of chips to be less than five microns thick.

Integrated circuit chips are built on large wafers, 30 centimeters or more in diameter. The wafers are typically 750 μm (micrometers) thick for mechanical stiffness during manufacturing. After the planar circuitry is completed, the wafers are "backlapped", ground down on the back side to make them thinner. Then they are sawn into individual die ( == chips ). The backlapping is a coarse grinding process, and variation in the process limits the thinness of the resulting die, but 50 μm thick is a typical result, good enough for cell phones and other volume-constrained products. The die can be made much thinner, as low as 20 μm or even 7.5 μm, for attachment to paperthin substrates in applications such as RFID tags. Such paperthin die are more flexible and more resistant to fracture, and the processes for making thin chips reliably will (hopefully) be widespread and very inexpensive when thinsats are produced by the billions.

The density of silicon is 2.33 g/cm3, so a 20 μm layer of processed silicon weighs about 4.7 mg/cm2, or about 20 square meters per kilogram (note: the silicon would be partly transparent, too thin for solar cells). A 300 millimeter wafer thinned to 20 μm weighs 3.5 grams and has an area of 700 cm2. Assuming a 2x markup for profit and yield loss $5000 processor wafer costs $15 per cm2 or about $3M per kilogram thinned to 20 μm . A $1600 memory wafer costs $5 per cm2 or about $1M per kilogram thinned.


This is an Intel Ivy Bridge CPU, with 4 processor cores and 1.4 billion transistors, attached upside down to a package. The chip is 1.6 cm2, and probably thinned down below 750 μm to improve thermal conductivity. If this die was thinned to 200 μm, the silicon would weigh perhaps 85 milligrams. If it was thinned to 50 μm, 34 milligrams, about 8 milligrams and 0.4cm2 per processor. A large Google data center might contain a million processors; about 2 kilograms of active CPU silicon - embedded in tons of substrate and packaging, and thousands of tons of circuit boards, racks, wiring and cooling water plumbing.

Server sky processors will be rather different than the Ivy Bridge CPU core - running at lower speed and optimized for power efficiency, they will more resemble Intel's processors for handheld devices, without the graphics processing and with radio sections that produce and receive differential intermediate frequency I and Q signals to and from external radio chips. They will also have additional error checking and redundant control logic to withstand radiation induced soft errors. Assume a 0.1 cm2 single processor die, $1.50 each

At this transistor density, 20 square meters of CPUs weighs a kilogram, costs $3M unpackaged, and contains 1.6E14 transistors


Dynamic Random Access Memory Hynix 62x93nm (31nm 6F?) DRAM cell. A gigabyte of RAM has an area of 0.6 cm2, including some periphery and error-correction processing. At 20μm thick, that is 3 mg/GiB, or 330TiB/kg, 2.9E15 transistors costing $1M after yield loss and profit

Solid State Flash Memory. Cross section of a 27nm Samsung NAND flash array. Intel and Micron offer a 25 nm, 64 gigabit, 1.31 cm2 3 level flash memory. At $5/cm2, that is $820/TiB. Thinned to 20 μm, that is 800mg/TiB, 1.2PiB/kg, 3.6E15 transistors/kg.

In April 2014, complete drives retail for $500/TiB, so the wafer prices quoted above are too high, a price war is causing sales prices below manufacturing cost, or the die cells have shrunk significantly. Lets assume 700mg/TiB, $500/TiB, 150cm2/TiB, a kilogram is 1.25PiB and 20m2, costing $625K

Memory will have additional logic to do error correction after access and before refresh. It will likely be optimized to run at higher power efficiency and lower speed than terrestrial applications like desktop CPUs


Google Data Center - est. 110 lb/ft2 including structure, power transformers, plumbing and rooftop chillers, 200,000 sq ft (two buildings plus auxiliary structures), 1 million kilograms.

This does not include the power generation and transmission infrastructure feeding the building, nor the fiber optic network it feeds, so the mass could be quite a bit higher to deliver the same function as a self-contained server sky constellation

A 256 core, 1 TiB flash, 64 GiB dram processor array at $10/g launch cost, active silicon only, NOT including thinsat substrate, solar cell, wiring, etc:



total area

total mass

chip cost

launch cost

256 processors


25.6 cm2

120 mg



512 GiB flash


75.0 cm2

350 mg



64 GiB dram


9.6 cm2

45 mg




110.2 cm2

515 mg


If this represents the capability of one thinsat, and an array of 7842 thinsats weighs 39kg, then multiply the above compute power by 7942 for a silicon launch cost of $40K and a thinsat launch cost of $390K, including power supply and radio ground link. Arrays share flash storage, so the flash memory capacity of the entire array would be 3.9 petabytes.

Intra-array bandwidth is limited, so frequently accessed items will be stored on many thinsats, some items cached in flash memory on all of them. Access to specific information items will follow a long tail power law distribution, with a small percentage of all stored information accounting for a large percentage of downlink traffic. Some rarely used items will be bit compressed and stored in only a few arrays, perhaps even on the ground. As the array count M288 approaches environmental limits, some of the rarely-used information may be stored in arrays in higher orbits producing less light pollution.

Alternative: A Slimmer Thinsat with Multipurpous chips

We will need 1000 radio power amplifiers, perhaps 4 per chip, but we do not need 250 processors. Imagine that we populate the thinsat with 250 die, each driving 4 radios and connecting to 4 nearest neighbors in a grid with high speed low voltage differential buses, but a mix of processors, flash, and DRAM. First, let's cut the flash way back - we have about 8000 thinsats in an array; if we want to store a ten thousand hours of video per array, at 10 GiB per hour of video, that is 100 PiB, or 128 GiB per thinsat. Still a lot. Early arrays may produce only one gigabit per second, this is mostly a distribution issue, we don't need that much processing per thinsat. Lets assume we can get by with a mere 16 processors per thinsat, with 8 redundant spares for failure (and normally powered down). RAM? Same deal. We will divide compute jobs up among the whole array, we can operate the processors on one thinsat SIMD or from small programs. Let's cut the total RAM per thinsat down to 8GB (with 4 redundant GB), and assume that 64 TB per 8000 thinsats is plenty. So, how much area is that?

Second Estimate



total area

total mass

chip cost

launch cost

24 processors


2.4 cm2

13 mg



128 GiB flash


18.8 cm2

100 mg



12 GiB dram


1.8 cm2

36 mg




23.0 cm2

149 mg



If we divide 2300 mm2 by 250 chips, that works out to about 9.2 mm2, a hair over 3 mm on a side. Let's add some periphery and drivers to that 0.1mm on a side is plenty - and we get 3.2 mm on a side. Rounding, that's 26 processor chips, 204 flash chips, and 20 dram chips per thinsat, all 3.2x3.2 mm with identical I/O. 10.24 mm2 per die. Extra multipurpose pins on each chip can be programmed to connect to SAW resonators for timing, electrochromic thrusters, or other functions.

7842 Thinsats

per Thinsat

per Array

Silicon Area

25.6 cm2

20.33 m2

Silicon Mass

120 mg

0.95 kg

Chip Cost



Est Thinsat Mfg Cost



5g Thinsat Launch Cost



Deploy Bus cost


Total Cost



Very Small Chips

Among the smallest manufactured chips are Hitachi's "µ-Chip"s.
















Press Release Local copy










No chip, a chip handling process instead





90nm SOI

Press Release Local copy

ChipMass (last edited 2014-06-30 05:38:33 by KeithLofstrom)