Integrated Circuit Mass
How Much does a Chip Weigh?
CMOS (Complimentary Metal Oxide Semiconductor) integrated circuit chips are made N type and P type MOS field effect transistors, wiring, insulators, on top of a silicon substrate. The zoo of devices on all varieties of integrated circuits includes bipolar transistors, diodes, capacitors, loop inductors, diffused and thin-film resistors, sometimes even special sensors like avalanche photodiodes. However, almost everything we do with server sky will involve advanced-process CMOS, with some DRAM ( Dynamic Random Access Memory ) using stack capacitors and some flash (block rewritable) EEPROM ( Electrically Eraseable Programmable Read Only Memory, which writes information by trapping charges in the insulators of MOS gates.
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These are all planar processes produced by photolithography. All structures are made by deposition and etching of materials, and are typically very thin, a few micrometers. High power integrated circuits, such as 150 watt microprocessors and GPUs, are somewhat thicker, because the uppermost layers of interconnect metal are thick and low resistance to handle up to 100 amps of power. The lower signal handling metal layers are thin and optimized for low capacitance wires, typically no more than twice as high as they are wide (a fraction of a micrometer). |
Server sky chips will use low power varieties of these advanced processes, with fewer metal layers and no fat upper layers because each chip will be small and use milliamps rather than amps. We can expect the thickness of the active layers of chips to be less than ten microns thick.
Integrated circuit chips are built on large wafers, 30 centimeters or more in diameter. The wafers are typically 750 micrometers thick for mechanical stiffness during manufacturing. After the planar circuitry is completed, the wafers are "backlapped", ground down on the back side to make them thinner. Then they are sawn into individual die ( == chips ). The backlapping is a coarse grinding process, and variation in the process limits the thinness of the resulting die, but 50 μm thick is a typical result, good enough for cell phones and other volume-constrained products. The die can be made much thinner, as low as 20μm or even 7.5μm, for attachment to paperthin substrates in applications such as RFID tags. Such paperthin die are more flexible and more resistant to fracture, and the processes for making thin chips reliably will (hopefully) be widespread and very inexpensive when thinsats are produced by the billions.